Use of Randomization in queues

SystemVerilog
, ,
2

In reply to Maniramadugu:

I think what you want to write is

module element;
 class abc;
   randc bit[7:0] a[8];
   constraint u_c { unique {a};}
 endclass
 initial begin
    abc b;
    b = new(); 
    if(!b.randomize()) $error("randomize failed");
            else begin
               $display ("Success");
               foreach(b.a[i]) $display("a[%0d] = %0d", i, b.a[i]);
            end
    end
endmodule