Use of clocking blocks in different types of testbench

SystemVerilog
1

Hi,

I’m trying to understand why clocking blocks are used in SV testbench compared to that of Verilog testbench but not used in UVM based testbench.
And how does this relate to event schedulers of both the languages.

Thanks
Sujith

2

when you say both languages, do you mean Verilog versus SystemVerilog? Clocking blocks are only in the SystemVerilog. UVM is not a language.

I would not say that people using UVM do not use clocking blocks.

3

do you mean Verilog versus SystemVerilog I meant a pure SV testbench vs testbench that uses UVM. Just for comparison.

I was looking at some examples of interfaces online where I saw that clocking blocks were not implemented in interface. In that case, how does the TB takes care of driving and sampling signals?

4

The same way the RTL design does–using nonblocking assignments to drive signals, and making sure all the sampled signals are also driven correctly.

Clocking blocks provide a layer of isolation from a variety of coding styles good or bad. They are not strictly necessary.