In reply to Daphn:
When you want to enforce the direction of an input port. Because of port collapsing, Verilog cannot enforce the flow of data through an input or output port when both sides of the connection are nets. It behaves like a single piece of metal on silicon.
When one or both side of a port connection are variables, a unidirectional continuous assignment gets inserted in the connection. This also means that when applying a force to the lower level module’s port, the force does not propagate back through the port in the opposite direction.