Usage of Var

SystemVerilog
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SystemVerilog has some funky defaults in order to be backward compatible with Verilog.

SystemVerilog added the concept signal kinds: nets or variables, that are distinct from data types. This allows you to add data types like structs and enums to wires.

When you declare the variables data_1 and data_2

logic data_1;
reg [31:0] data_2;

This is implicitly equivalent to

var logic data_1;
var reg data_2;

Similarly, when you declare the net data_3;

wire data_3;

This is implicitly equivalent to

wire logic data_3;

You can also now do

struct { logic  parity,
         logic  [31:0] word
       } wordp_t;
wire wordp_t A;

The var keyword is usually not needed, but there are at least two places it becomes necessary.
When you use the type() operator, the var keyword is necessary to parse the declaration.

reg [2:0] A;
var type(A) B; // declare variable B the same type as variable A

In a port list, the default for ‘input logic A’ is to declare A as a wire, not a variable, so you would do

module mymod(input var logic A);

to make it a variable.

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