$urandom_range('0, '1) gives single bit output

SystemVerilog
5

In reply to dave_59:

Thanks Dave. So when the LRM says:

No other contexts shall be considered assignment-like contexts. In particular, none of the following shall be considered assignment-like contexts:
— A static cast

Does this mean that the code


typedef int unsigned uint;
var_a = $urandom_range (uint'('1));

should give the same result as the original question?