In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks. Actually for this case, I cannot use $rose as req can be high at cycle 6th and I would want the assertion to check for ack from then on.
clk 1 2 3 4 5 6 7 8
req 0 1 1 1 1 1 1 1
ack 0 0 0 0 1 0 0 1
In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks. Actually for this case, I cannot use $rose as req can be high at cycle 6th and I would want the assertion to check for ack from then on.
clk 1 2 3 4 5 6 7 8
req 0 1 1 1 1 1 1 1
ack 0 0 0 0 1 0 0 1