Unique if working principle

SystemVerilog
1

  1. program tb_top();
    int a,b;
    initial begin
    a = 10;
    b = 15;
    unique if((a == 1) && (b == 7)) $display(“ONE”);
    else if((a == 1) && (b == 7)) $display(“TWO”);
    end
    endprogram: tb_top

  2. program tb_top();
    int a,b;
    initial begin
    a = 10;
    b = 15;
    unique if((a == 1) && (a == 7)) $display(“ONE”);
    else if((a == 1) && (a == 7)) $display(“TWO”);
    end
    endprogram: tb_top

Both conditions are the same in 1 and 2. But I am not getting any compilation warnings that both are not unique. Can any one explain?

  1. program tb_top();
    int a,b;
    initial begin
    a = 10;
    b = 15;
    unique if((a == 1) || (a == 7)) $display(“ONE”);
    else if((a == 1) || (a == 7)) $display(“TWO”);
    end
    endprogram: tb_top

In 3rd one It throws a compilation warning that both are not unique.

I am confused

2

I get run-time warnings for all three cases. You may be running into tool specific issues.

3

yeah. I am getting runtime warnings that none of the condition is true.
Not they are not unique.