Hi, I want to control our channel timing during data transfer with assertion and also i create a assertion with genvar up to channel number. proerty ch_timing(param1,param2,param3); @(posedge clk) .... condition..... endpropery generate for(genvar i = 0; i<ch_number; i++) begin: gen_label_…

In reply to asvn : With the tool I am using I see the path.assertion_label For example, /top/genblk[0]/my_assertion_label /top/genblk[1]/my_assertion_label /top/genblk[7]/my_assertion_label Why can’t your testplan use the [i] and make more generic; after all, it’s English Ben

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Uniqe assertion label name

SystemVerilog

ben2 February 27, 2018, 9:15am 3

In reply to asvn:

That’s a tool dependent thing. gen_blok[i].asssertion_label // i==1, 2, 3, …
Ben