In reply to ben@SystemVerilog.us:
Ben,
There is a difference in the 2 codes, in my example the simulation ends at T:89.
In my case ( edalink ) ::
Although the antecedent is true at T:85 for 2nd $rose(read), the consequent doesn’t began evaluation till T:95 ( due to |=> ).
This means the strong operator isn’t in effect , so why does assertion fail for 2nd time at T:89 ( when simulation ends ) ?
The 1st failure at T:85 is expected whereas the 2nd one at T:89 isn’t.
In your code ::
The 2nd error is as per expectation due to strong operator being in effect from T:95.
Yet I observe fail == 1 and not fail == 2 during end of simulation at T:129, why is it so ?