Unexpected SVA failure using s_until_with

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Ben,
Although the flag ‘fail’ in the dump is seen as 1, the output log using Questa shows:
**# Assertion fails at T: 85

** Note: $finish : testbench.sv(47)

Time: 129 ns Iteration: 0 Instance: /tb

Assertion fails at T:129**

EDIT: In my code simulation ends at T:89. The output log on Questa shows:
**# Assertion fails at T: 85

** Note: $finish : testbench.sv(43)

Time: 89 ns Iteration: 0 Instance: /tb

Assertion fails at T: 89**