Ran your code with different vendors and got different results.
What you have is a tool issue. Rerun your code with various vendors and see what you get.
We do not address tool issues in this forum, thus I’ll not name any tool that has the issue.
Note that the “state” variable, when used in the property of the assertion, is the sampled value of state. When used in the action block it is incremented value performed in the NBA region. If you need the sampled value to be displayed in the action block then you need to the $sampled(variable_name). BTW, your tool may not support $sampled(state.name)
The correct result is
0, state = STATE1
# 25, state = STATE2
# 35, Start property sequence s2_7 , state = STATE2
# 35, state = STATE3
# 45, Starting sequence s2_7 , state = STATE3
# 45, state = STATE4
# 55, state = STATE5
# 65, state = STATE6
# 75, state = STATE7
# 85, state = STATE8
# 95, Property s2_7 is asserted.
# 95, Sequence s2_7 has finished
# 95, state = STATE1
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy