Understainding LRM: why IntA= -'d12/3 yields 1431655761?

SystemVerilog
1

I could not understand the example in LRM.
“11.3.3 Using integer literals in expressions” says:

Note that -12 and -'d12 both evaluate to the same two’s-complement bit pattern, but, in an expression, the -'d12 loses its identity as a signed negative number.

int IntA;
IntA = -12 / 3; // The result is -4
IntA = -'d 12 / 3; // The result is 1431655761

( 1431655761 == 0x55555551, so value before dividing by 3 is 0xFFFFFFF3 )

I could not understand why the result is as such. Does anyone help me understand how it works?
I thought as below. Is this correct?

  1. As IntA is 32bit, 'd12 is internally treated as '32h0000_000C
  2. – ('d12) is the same as ~('d12), so -'d12 is treated as 32’hFFFFFFF3, thus result is 1431655761.

Thanks

2

BTW, the 2’s complement of a number N is ~N+1.

This example might explain what is going on better

module top;
  int IntA;
  initial begin
    IntA = -12;
    $display("%h %d", IntA,IntA);
    IntA = -'d12;
    $display("%h %d", IntA,unsigned'(IntA));
    IntA = -12 / 2; // The result is -4
    $display("%h %d", IntA,IntA);
    IntA = -'d12 / 2; // The result is 1431655761
    $display("%h %d", IntA,IntA);
  end
endmodule

Displays:

# fffffff4         -12
# fffffff4 4294967284
# fffffffa          -6
# 7ffffffa  2147483642