Unable to figure out fix for race condition in uvm driver: any help is very much appreciated

In reply to chr_sue:

I’ve added now the reset signal to the input of the clocking block but the race condition still remains. By the time that the driver executes:


if(delay==0 && vif.cb_write.b2b_halt==0) begin //when the simulator reaches here the value of this signal isn't updated yet

the value of the signal isn’t updated yet.