In reply to chr_sue:
So, the DUT tells the UVM driver to stop sending data by asserting the ‘halt’ signal. The RTL sets this signal to ‘1’ when it doesn’t have more storage available.
Let’s say that the previous cycle the RTL received data and that has filled the data buffer in the RTL. This would mean that the current cycle the RTL would set the ‘halt’ signal to ‘1’.
The driver sends data to the RTL in the rising edge of the clock. If the driver doesn’t read the value of the ‘halt’ signal until the negedge of the clock this would mean that the current cycle the driver would send data to the RTL even when the ‘halt’ signal was asserted.
I did try using negedge as well in the clocking block, but it doesn’t fix the problem.