In reply to chr_sue:
Yes, the signal comes out correctly from the DUT. I’m guessing this happens due to the SV scheduler.
I’ve checked the waves and also set breakpoints in the code.
I also see the DUT generates the signal correctly because when I don’t use the clocking blocks and set a small fix delay after the rising edge of the clock by the time the execution of the code reaches:
if(delay==0 && vif.cb_write.b2b_halt==0) begin //when the simulator reaches here the value of this signal isn't updated yet
the driver sees the correct value in the ‘halt’ signal.