Type casting with signed arithmetic

SystemVerilog
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3

In reply to dave_59:

In reply to prashantg:
The problem is the fractional part of d is not exactly 0.5. Display using “%.17f”.
There is also rounding in the conversion from binary to decimal. Use $realtobits to see the internal binary representation.

Thanks, Dave for the insight.

Some additional queries:

  1. Decimal place till which a single expression is calculated?
  2. Is this behaviour consistent across simulators?
  3. Does type casting from real to int i.e. int’ use $realtobits?