In reply to dave_59:
Thanks, Dave! Your post is kind of huge. Coming from a C++ perspective and the fact that SystemVerilog supports the `include preprocessor directive, it’s totally counterintuitive to hear that the preferred approach to compose a class is to put the interface and implementation in the same file (for advice on doing the opposite in C++ see the references section of the wikipedia entry on Class Implementation file).
Is there any chance a guideline could be added to the SV/Guidelines section of the UVM Cookbook?