In reply to qais:
In reply to kiteloop:
why don’t u use one monitor and you can specify the number of analysis ports you need. Just extend your monitor class from component so you can have all the analysis ports needed.
uvm_monitor doesn’t implement any analysis ports anyway, it just extends from uvm_component.
But the problem is not about the analysis ports. It’s about what is the best practice with respect to monitoring the input and output bus of a very similar interface, and how to implement the most ‘UVM-friendly’ solution.