In reply to dave_59:
// --------------------------------------------------------------------------------
timescale 1 ps / 1 ps //include “dct_edif.edn”
(* STRUCTURAL_NETLIST = “yes” *)
module dct_dut
(CLK,
RST,
xin,
z_out);
input CLK;
input RST;
input [7:0]xin;
output [10:0]z_out;
its in verilog file and other .edn file we got at time of netlist conversion so i replaced rtl file with netlist file. i add xilinks library files added in project.
what I have to do now ?? if you can provide GLS verification small example. that’s will be very helpful.