Turn Off All Assertions Inside Generate Block

In reply to Reuben:

I have posted my inputs here in-order to help reduce your debug time. Even I have the same questions. I neither tried with other simulators, nor I followed up with EDA vendor at that time. If you happen to track the issue with EDA vendor, just post the answers for your questions here for future reference. Or, let us wait for the SV language experts here to comment.