Turn Off All Assertions Inside Generate Block

SystemVerilog
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2

In reply to Reuben:

I encountered a similar issue before (with VCS). I resolved this by,

  1. Adding the hierarchy in double quotes (this solved only compilation issue, but during simulation tool reported “path not found in the design”).
    $assertoff(0, “my_top.my_assertion.my_gen_block[0]”);
  2. Then, I specified the next level of hierarchy under the generate named block.
    Ex: $assertoff(0, “my_top.my_assertion.my_gen_block[0].assertion_A”);

In my case, all assertions were in another module which was instantiated under generate named block.
Ex: $assertoff(0, “my_top.my_assertion.my_gen_block[0/1/2].assert_module_inst”);.

It is good to load the design without having “$assertoff” statements first to check the exact hierarchy in the compiled/elaborated database and try using the path directly.