Trying to access internal design signal by using an abstract interface

UVM
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5

In reply to dave_59:

Hi Dave,

This is how I have written the bind statement.
Right now accessing only one signal for testing purpose.

bind in2_module : tb_top.design_top.in1_module.in2_module probe_intf m1(internal_signal_1);
bind in3_module : tb_top.design_top.in1_module.in2_module.in3_module probe_intf m2(internal_signal_2);

I will check the tool version as well.

Thanks.
Karan