Triggering Covergroup Sampling via SVA

In reply to ben@SystemVerilog.us:

Thanks for the detailed explanation Ben .

(1) Via @( Detect_EOP ) some tools correctly sample auto[5] while others still cover auto[0] unfortunately .

An alternative would be calling sample() function from the subroutine ( instead of triggering the event in subroutine )

This would mean there is no sampling event defined for covergroup i.e covergroup frame ;

(2)

Therefore, framelength is still 0.

LRM 16.11 mentions :: " Assertion evaluation does not wait on or receive data back from any attached subroutine. "

Does this mean the display at the end of the sequence ( "framelength is %0d " ) execute ( in Observed Region ) before the function ’ trigger_cg ’ is called ( in Reactive Region ) ?

( Although the subroutine call appears before the $display )