Hi,
I have following cover point
coverpoint (sigX, sigY}) {bins hit = (2’b10=>2’b00[*1:10]=>2’b01); bins hit2 = (2’b01=>2’b00[*1:10]=>2’b10 );}
Basically I want this two asynchronous events to come within 10 clk period.
Now I want to cover the whole range [*1:10]. In simple words, I want this events to come at 10 clk, 9 clk, 8 clk,…,0 clk time difference.
Is there any option predefined in System Verilog for this? How do I go about it?
I was thinking if I give the option.at_least=100 and cover point is hit than I can assume that it would have covered 1:10 range. But this is relying on randomness.