Toggling DUT output check in SVA

SystemVerilog
1

Dear all,
How to write an assertion check for this:
Ques:- Suppose if we are giving 101100101 bit streams to DUT input, whenever input bits are toggling (i.e 1->0 or 0->1), the output of the DUT get pulse.
How to write assertion checker for this?

Can anyone give me the code snippet ?

2

Assuming ‘ip’ is the serial input to DUT which is sampled on each posedge of clk and
‘op’ is asserted on same posedge of clk whenever ‘ip’ toggles from previous input

toggle:assert property( @(posedge clk) $changed(ip) |=> op ) ;
3

Hi @MICRO_91
Thanks for your quick reply.
I am not aware about $changed.
I tried this:-
toggle: assert property(@(posedge clk) ($rose(ip)||$fell(ip)) |=> op);
Any problem with this code?

4

LRM 16.9.3 ::

$rose ( expression [,  [clocking_event] ] )
$fell ( expression [,  [clocking_event] ] )
$stable ( expression [,  [clocking_event] ] )
$changed ( expression [ ,  [ clocking_event ] ] )

— $rose returns true (1'b1) if the LSB of the expression changed to 1. Otherwise, it returns false
(1'b0).
— $fell returns true (1'b1) if the LSB of the expression changed to 0. Otherwise, it returns false
(1'b0).
— $stable returns true (1'b1) if the value of the expression did not change. Otherwise, it returns
false (1'b0).
— $changed returns true (1'b1) if the value of the expression changed. Otherwise, it returns false
(1'b0).

$rose , $fell works only on lsb whereas $stable , $changed work on the entire expression.
So if ‘ip’ were more than 2-bit wide you would have to write

$rose(ip[0]) || $fell(ip[0]) || $rose(ip[1]) || $fell(ip[1]) |=> op);