To check for ready de-assertion between sop and eop

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Thanks Ben for your reply.

  1. Can you please tell what does this mean in assertion here?

rdy[->1]

  1. Also , if between one sop and eop , ready gets de-asserted multiple times, will this assertion be able to check for that ?
    Because assertion start time would be from $rose(sop) and after rdy and valid de-assertion , this would wait for eop to come , I am not sure if it will check for another ready de-assertion ?

Thanks!