In reply to ben@SystemVerilog.us:
In reply to gani:
// 1800:
// $width ( controlled_reference_event , timing_check_limit , threshold [ , [ notifier ] ] ) ;
// The $width timing check reports a violation in the following case:
// threshold < (timecheck time) - (timestamp time) < limit
$width(posedge clk,10); // >I am not seeing any failure why???
Because, per 1800:
The pulse width has to be greater than or equal to limit in order to avoid a timing violation,
but no violation is reported for glitches smaller than the threshold.
You could use an assertion to check for width. From my SVA Handbook 4th Edition I show an approach that you can use to meet your requirements. This example can be used as a guide.
10.34 Measuring clock periods
User’s requirement: Check that the duty cycle of a clock is within acceptable limits.
The concept is simple: based on clock edges, measure the widths in which the clock is high and low, and compare the difference against an acceptable tolerance. The use of realtime type provides more accuracy. When using a concurrent assertion, local variables are used to hold the measured values. A multiclocking approach is used to trigger on each edge of the clock. module timem; // /ch10/10.34/timem.sv
import uvm_pkg::*; `include "uvm_macros.svh"
module timem;
timeunit 100ps; timeprecision 100ps;
initial $timeformat(-9, 5, " ns", 10);
bit clk, a, b;
bit[1:0] delta;
initial forever begin
if (!randomize(delta)) `uvm_error("MYERR", "This is a randomize error")
#(4.8ns + delta*0.1ns) clk=!clk;
end
property period_chk;
realtime current_time, deltat; // deltat used for debug, as a temp
('1,current_time = $time ) ##1
(1, deltat=current_time) ##0 deltat == 10ns;
endproperty
ap_time: assert property(@(posedge clk) period_chk);
property period_chk2;
realtime current_time, deltat;
('1,current_time = $time ) ##1
(1, deltat=current_time) ##0 (deltat >= 9.99ns && deltat<= 10.01ns); //
endproperty
ap_time2: assert property(@(posedge clk) period_chk2);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
If it is the case,it is same for all other timing checks right?,Then what is the point of verifying these checks using timing checks.?
This check is only valid threshold < (timecheck time) - (timestamp time) < limit
We are verifying only half of it rt?if i am wrong please let me know.
2)Please explain this equation // threshold < (timecheck time) - (timestamp time) < limit
Thanks,
Nagendra.