In reply to Suman Valsange:
It’s not possible and not necessary.
In discrete event simulation, time gets represented by an integer, 64-bits in SystemVerilog. Converting decimal numbers to binary fractions does not always wind up with a number that fits into 64 bits, or even a rational number. You would need at least
dly_time = 0.20100502512ns;
You might want to see https://floating-point-gui.de/
But there is no need to get this level of accuracy in a digital logic simulation as long you as know what the simulated clock frequencies come out. The only thing that really matters is the relative ratios between what you are calling the 2.4875Ghz clock, and any other clocks that are some multiple/fraction of it.