The timescale contains timeunit and timeprecision elements to specify the unit of measurement for time and precision of time in specific design elements. The time_precision argument shall be at least as precise as the time_unit argument; it cannot specify a longer unit of time than time_unit.
Referring to IEEE 1800-2012 section 13.4.2, changing timescales in modules could cause very different simulation results, depending on timevalues specified in different modules.
If multiple timescales are provided, the last timescale persists. Hence it depends on the compilation order of files. SystemVerilog provides timeprecision keyword to set the precision of time within a module. Use timeprecision 100fs; in your module to override the default timeprecision.
So, here you might want to use timescale as 1ns/100ps. Also, the clock toggling should be done using ~ (tilde) operator. The ! (negation) operator is boolean negation, while ~ (tilde) is bitwise negation.
I have created an example at EDAPlayground Link. Observe that clk is generated using default timeprecision (that is, 1ns), while internalclk is generated using overridden timeprecision (that is, 100fs), thereby giving 1GHz clock frequency.