In reply to ben@SystemVerilog.us:
Ben ,
Could you please elaborate on “If end of Sim at the ##1 1 |->”
Does it mean at exactly the ##1 OR between A being true and the next clock tick ?
Let’s take the following example ::EDA_LINK2
There are 4 cases ::
(1) Simulation Ends after 1st Clock tick ( +define+M1 )
(2) Simulation Ends at exactly the 1st Clock tick ( +define+M2 )
(3) Simulation Ends after 2nd Clock tick ( +define+M3 )
(4) Simulation Ends at exactly the 2nd Clock tick ( +define+M4 )
**Antecedent isn’t in progress for all these 4 cases i.e
Evaluation of Antecedent is complete and it has Non - Empty match for ALL 4 cases** ,
Ideally should I observe a Failure for ALL 4 cases ?
**Also does the LRM touch upon this ? I tried looking in the LRM Section 16.12.2 Sequence property , however I couldn’t find anything related to this .
**