This keyword

SystemVerilog
4

In reply to Shiv_coder:

Hi,

I had modified your code a bit, have a look below.

class base;
int a;

function disp();
$display(a);
endfunction
endclass


class ext extends base;

int xyz;



function disp1();
  this.a=xyz;
  this.disp();
endfunction

endclass



module tb;
ext a1 = new();

initial begin
  a1.xyz=10;
a1.disp1();
end

endmodule

in above, value 10 will be displayed.

if we modify the extended class to include another function of name disp, then the function disp in base class is hidden

class base;
int a;

function disp();
$display(a);
endfunction
endclass


class ext extends base;

int xyz;


function disp();
$display("Extended Display");
endfunction


function disp1();
  this.a=xyz;
  this.disp();
endfunction

endclass



module tb;
ext a1 = new();

initial begin
  a1.xyz=10;
a1.disp1();
end

endmodule

for above output will display text Extended Display.

to access disp function from base class, then we use super keyword as below.

class base;
int a;

function disp();
$display(a);
endfunction
endclass


class ext extends base;

int xyz;


function disp();
$display("Extended Display");
endfunction


function disp1();
  this.a=xyz;
  super.disp();
endfunction

endclass



module tb;
ext a1 = new();

initial begin
  a1.xyz=10;
a1.disp1();
end

endmodule

the above code will display value 10