The timing period check

SystemVerilog
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1

Hi all,
I am having a simple checker in my module that samples time at different events and compares the expected and actual value, my waveshape shows the exact value, my prints show the exact value, but my Checker is always failing and giving an error. Unable to figure out the issue. Seems like the sampling time issue, but how do I figure it out and fix it ?

Thanks in advance.

2

In reply to Saraswati:

Checker can also be correct! What is the error message you are getting? How you are displaying the timing value? Time precision issue might be there with displays. Also, what data type are you using to store the time information?

3

In reply to mayurkubavat:

Hello,
Yes it was an issue with Time precision, when I matched it, it worked, thank you:)