The function 'foo' is not a valid constant function error occurs only in large builds

SystemVerilog
6

just figured out the issue.

this is an example of the code that failed:


module top();

logic [2:0] in;
logic [2:0] out;

foo foo_i(
    .*
    );

endmodule

module foo (
    input logic [2:0] in,
    output reg [2:0] out
);

generate
  if(1)
    `include "foo.svh"
endgenerate

logic [32:0] wdata_all;

assign out = in - P;

always_comb begin
  $display("P = 0x%x",P);
end
endmodule

function integer count_1s;
  input [32:0] in;
  input integer count;
  integer idx;
  begin
    count_1s = 0;
    for(idx = 0; idx<count; idx=idx+1)begin
      if(in[idx])
        count_1s = count_1s+1;
    end
  end
endfunction

notice that we were including the foo.svh inside a generate statement. This is where the problem lies. If we remove the generate statement it compiles just fine.

Edit: it helps to know that the function is located in foo.svh