In reply to selmenna:
OK, I see you are a newbee in UVM :-)
There is no ONE flow to do this. But there are a few guidelines you should follow. I see 2 approaches:
(1) you should take part in a UVM Course if you are familiar with SystemVerilog.
(2) If you have time you can exercise the UVM on your own. Visit Doulos KnowHow.
There you’ll find a lot of important stuff.