Techniques to reduce simulation time in OVM

OVM
1

Hi,
I am using OVM for Developing TBs.
I want to know is there any way to reduce simulation time?
Some optimization techniques in general?
Please share your experiences so that everybody can follow such tips.

Thanks in advance.
Jithin

2

The biggest tip I can offer you with the OVM/UVM is to avoid the field automation macros `ovm_field_*. See MacroCostBenefit | Verification Academy.

The other tip for SystemVerilog, or any other language is to have code reviews. The simple task of explaining your code to someone else can uncover many inefficiencies. For example, you might be iterating over an array element by element or bit by bit when you be using a single statement. Inefficient loops are usually the easiest to address.

3

In reply to dave_59:

Thanks Dave.

4

The first thing to do is figure out what is consuming your simulation time – and that means profiling the code. All simulators provide this capability, and it’s something a lot of verification engineers ignore altogether – or ignore until late in the design cycle. I like profile my simulation env early in test bench bring-up.

Except under rare circumstances, I would expect the vast majority of simulation time should be consumed by the DUT. If that’s not the case, you have a problem, and I would start with the “low hanging fruit” from the profiling results.

Once you have done all you can w/the testbench code, there are tricks you can do w/the RTL. For example, suppose your design in a 16-port Ethernet switch. For some sims, it may be worthwhile to force gate the clocks to some of those – say 12 ports, and restrict your stiumulus to route packets thru the remaining 4 ports. In this way, you can drastically reduce unecessary simulation events and speedup sims.

Finally, ensure that you do not run sims w/waveform dumping enabled unless needed. For regressions, I run all my sims w/out waveform dumping enabled. When I encounter a failure, my regression scripts automatically rerun the failing test/seed w/waveforms enabled. This is the best of both worlds – my sims run as fast as possible when passing (and consume less disk space), and at the same time, I have waveforms ready for debug when needed.

Good Luck –
Dan

5

In reply to mog71:

Thank you Dan for your valuable advice.

Can I know more about profiling the code. I am using Questasim 10.0c for simulation.
It will be really good if i get some examples in this regard.

Regards
Jithu

6

In reply to Jithin-vlsi:

Look in the Questa User Guide Profiling Performance and Memory Use > Viewing Profile Details and in the example directory

<install>/examples/tutorials/verilog/profiler/
7

In reply to dave_59:

Thank you

8

Can anyone help out with save/restore simulation at various checkpoints…

Any other way to optimise simulation time…

I am using Synopsys VCS for simulation