The biggest tip I can offer you with the OVM/UVM is to avoid the field automation macros `ovm_field_*. See MacroCostBenefit | Verification Academy.
The other tip for SystemVerilog, or any other language is to have code reviews. The simple task of explaining your code to someone else can uncover many inefficiencies. For example, you might be iterating over an array element by element or bit by bit when you be using a single statement. Inefficient loops are usually the easiest to address.