In reply to ben@SystemVerilog.us:
related to this topic: PostPosted: Wed Aug 27, 2014 12:28 am Post subject: UVM scoreboard/monitor/predictor or SVA? Reply with quote Edit/Delete this post Delete this post
Interesting discussion about usage of scoreboard/monitors/predictors and SVA
https://verificationacademy.com/forums/uvm/any-idea-uvm-environment-general-counter-design
My summary point: A scoreboard / predictor / assertions are all techniques to implement a verification or checking that the design meets the requirements. In effect, they are all “assertions”, in the general sense, in that they assert or state/check that indeed everything that the DUT has experienced so far is indeed OK.
UVM puts a big hoopla about the scoreboard/monitor approach; but, as Gordon and I mentioned, an assertion language (e.g., SVA) is a methodology that is very efficient from a coding viewpoint because it skips those steps of monitoring and predicting the results. SVA does not work too well in all cases, but for many cases it does a fairly good job, and it should not be discounted, just because it is “NOT UVM”.
Another advantage of SVA is that it clarifies the requirements, something that should be done prior and during the design process.
I demonstrate the usage of assertions using an activity counter model
Ben SystemVerilog.us