Task usage using Non-blocking assignment

SystemVerilog
4

In reply to dave_59:

Dear Rishab,

Please find the code below executed as a .sv file.

reg [7:4]width,d1,d2;
	reg clk;
 

  task automatic t1(input [7:4]f,ref [7:4]a2  );
    begin
      d1 <= f;
      a2 <= d1;
    end
  endtask


 always@(posedge clk)
   begin
     t1(width,d2);
   end    

   initial
     begin
       clk = 1;
       width = 4'd6;
       forever #10 clk = ~clk;
     end

Observation : Error : LHS in non-blocking assignment may not be an automatic variable.

Please let me know if there is any mistake in my code.