In reply to saritr:
As you already know, the test loop won’t iterate until all three sequences complete. If things are not completing in a timely manner, one or more of those sequences is to blame.
I’d start by looking at the shared sequencer.
Since both axi_seq_i and axi_seq_4_dds_i are running on the same sequencer, the sequencer will apply the UVM_SEQ_ARB_FIFO arbitration, and pull transaction items interchangeably from each sequence. If you specifically need the tx_lin_int_big_sm_diff_sequence to send all 100 transactions, have the sequence call the ‘lock’ method (of m_sequencer), and unlock when sequence is complete.