SystemVerilog - virtual class implementing interface - compilation error when interface functions not at least redeclared in virtual class - why?

SystemVerilog
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In reply to nachumk:

Thanks for pursuing this. I think sections 8.26 and 8.26.7 can interpreted as conflicting rules. 2 of 4 tools on EDAPlayground have come to different conclusions. I will have to take this to the SystemVerilog IEEE committee for clarification.

I think these rules come directly from Java interfaces to make a more formal commitment to eventually implementing the method.