SystemVerilog: Solve before constraint on random child classes

SystemVerilog
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2

In reply to sharatk:

I relaxed my constraint a little bit. Now the next index only depends on previous index and I do not have to use the function. It seems to work well.


class b;
    rand bit A;
    rand bit [1:0] B;
endclass
class c;
    rand b arr[];
    constraint constraints_c {
        foreach(arr[i]) {
            if(i>0) {
                if(arr[i].A == arr[i-1].A)
                    arr[i].B != arr[i-1].B;
            }
            arr[i].A == 1;
        }
    }
    
    function new;
        arr = new[10];
        foreach(arr[i])
            arr[i] = new;
    endfunction
endclass

What is it with the function? Is it tool limitation or LRM/language quirk?