Systemverilog Multi-macro Usage

SystemVerilog
1

Hello, is there any way to add multiple macros after ifdef, like ifdef XXX || YYY ? Or is there any concise code that can achieve a similar function?
Thanks!

2

The IEEE 1800-2023 SystemVerilog LRM added this capability and some tools (like Questa) already support it. You need to put the expression in parenthesis.

`ifdef (A && B)
   // code for AND condition
`endif

`ifdef (A || B)
  // code for OR condition
`endif

Without this feature, you would need to create an intermediate macro

// AND
`ifdef A
    `ifdef B
        `define A_and_B
    `endif
`endif
`ifdef A_and_B
    // code for AND condition
`endif
// OR
`ifdef A
    `define A_or_B
`endif
`ifdef B
    `define A_or_B
`endif
`ifdef A_or_B
    // code for OR condition
`endif