Systemverilog : multi dimensional associative array with second dimension as string is not working within constraints

SystemVerilog
1

Hi,
I have this associative array of 2 dimensions with second dimension as string:
int arr[int][string];

I have this constraint:

  constraint c_c {
    foreach(arr[i])
      foreach(arr[i][s]) {
      if(uvm_is_match("abcd",s)) {   <- line 37
         found == 4567;
      }
    }
}

with this, I get this warning+error:

Warning-[SV-IVPSA] Integral value passed to string arg
testbench.sv, 37
Value of integral type is passed to the argument of type string.
The following expression is incompatible with the formal parameter of the
function. The type of the actual is ‘longint unsigned’, while the type of
the formal is ‘string’. Values of integral type can be assigned to a string
variable through cast.
Expression: s
Source info: uvm_pkg::uvm_is_match(“abcd”, s)

Error-[ATMC] Argument type mismatch in constraints
testbench.sv, 37
$unit, “uvm_pkg::uvm_is_match(“abcd”, s)”
Formal/Actual argument type mismatch for the #2 argument of function call.
If a formal argument is of type string, then also the actual must be of type
string.

Why is the second dimension being treated as a longint instead of string ?

2

I believe you’ve encountered a tool-specific issue. However, the correct syntax for writing this code is:

 constraint c_c {
      foreach(arr[i,s]) {
        if(uvm_is_match("abcd",s)) {  // <- line 37
         found == 4567;
        }
      }
    }