In reply to arquer:
The generate/endgenerate keywords were made optional in Verilog IEEE Std 1364-2005. The compiler can tell from the context whether for, if, and case statements are procedural or represent a generate block.
What’s really amusing/annoying are the assertions that follow the code you posted wrapped in three layers of guards: 1) a pragma comment, 2) a conditional compiler directive, and 3) a generate-if
// synthesis translate_off
`ifndef DISABLE_XPM_ASSERTIONS
if (SIM_ASSERT_CHK == 1) begin: assert_rst
always @ (posedge wr_clk) begin
assert (!$isunknown(rst)) else $warning ("Input port 'rst' has unknown value 'X' or 'Z' at %0t. This may cause the outputs of FIFO to be 'X' or 'Z' in simulation. Ensure 'rst' has a valid value ('0' or '1')",$time);
end
end : assert_rst
`endif
// synthesis translate_on
I don’t understand why people use pragma synthesis on/off comments when conditional compiler directives are so much easier for tools to work with (comments get stripped away by many pre-processors. Even easier is to write the assertion by itself and there are control constructs to turn on/off assertions without needed any guards.
assert property (@(posedge clk) !$isunknown(rst)) else $warning ("Input port 'rst' has unknown value 'X' or 'Z' at %0t. This may cause the outputs of FIFO to be 'X' or 'Z' in simulation. Ensure 'rst' has a valid value ('0' or '1')",$time);