SystemVerilog $feof()

SystemVerilog
8

Content of data_file:
08802000 ee69_0a75_3403_a586_cbcf_9dea_5cae_9e60
8802010 4c96_921f_6724_2263_fef5_c45c_7608_8499
8802020 8b02_143a_f6a8_1cea_33b5_5542_67fb_b654
8802030 973b_b697_7a39_f23c_3028_7282_2af2_92b8
8802040 9258_6c5b_7637_972a_5ec6_569c_addb_9051

    file = $fopen("data_file.txt","r");
      while (!$feof(file)) begin
          c = $fscanf(file,"%h %h",addr,data);
	  $display("addr:%h <<< -- >>> data:%h",addr,data);
      end

Output :
addr:08802000 <<< – >>> data:ee690a753403a586cbcf9dea5cae9e60
addr:08802010 <<< – >>> data:4c96921f67242263fef5c45c76088499
addr:08802020 <<< – >>> data:8b02143af6a81cea33b5554267fbb654
addr:08802030 <<< – >>> data:973bb6977a39f23c302872822af292b8
addr:08802040 <<< – >>> data:92586c5b7637972a5ec6569caddb9051
addr:08802040 <<< – >>> data:92586c5b7637972a5ec6569caddb9051

Last dat getting twice… Can anyone please explain me why last data is getting twice here.

Thanks,
Mukesh