SystemVerilog $feof()

SystemVerilog
13

In reply to dave_59:

Hi Dave,
Thanks for reply, please find the below snippet.

file1:
FF: A1 B1
FE: A2 B2
FD: A3 B3
FC: A4 B4

file2:
EF: A1 B1
EE: A2 B2
empty line…
EC: A3 B3

I want to compare 1st line of file1 with 1st line of file2, similarly 3rd line of file1 has to be compared with 4th line of file2 by skipping empty line(3rd line of file2).

task compare_files(input string ip_file,op_file);

    fd1 = $fopen(ip_file,"r");
    fd2 = $fopen(op_file,"r");
    fd3 = $fopen("cmp.out","w");

     while ($fgets(file1,fd1) && ($fgets(file2,fd2)) && (!$feof(fd1)) && (!$feof(fd2))) begin

	if($sscanf(file1,"%x: %x %x",addr1,data1,data2)==3)begin
	 data_final1 = {data1,data2};
	end

	
	if($sscanf(file2,"%x: %x %x",addr1,data1,data2)==3)begin
	data_final2 = {data1,data2};
	end

	//here I want to skip to the next line, if scanned line of fd2 is empty.
	//How to get the next line of fd2 ??
	//Aim is to compare the data_final1 and data_final2.

	//I achieved the aim by using associative array. 
	//But I want to know how to get next line without using continue statement in while loop.

	end

endtask:compare_files