In reply to Guy S:
Thanks for the additional information but I still do not understand how this relates to UVM. Are you trying to integrate this into an existing UVM testbench, or trying to develop a new one? It is fairly straightforward to get the adsp_v_read/write tasks to emit UVM sequences/transactions.
Regardless of whether you are using UVM or not, we need to understand how the interrupt service routine affects the DSP transactions in flight. Is the ISR a separate process? Are the transactions suspended during the ISR, or do they need to be restarted? Or can the interrupt only be serviced in between transactions?
There are different ways to handle each of these situations, and as I mentioned above, sometimes you have to make tradeoffs to model what is actually required in verification. I’m not sure if you are able to get into enough detail in this forum, so you may want to seek out local advice from your tool vendor.