SystemVerilog Constraint to populate unique values into a 2d fixed-size array without using the unique keyword

SystemVerilog
,
2

In reply to sfenil1804:

The foreach loop you are using is not legal syntax for the very problem you are running into. You are only allowed one set of [] brackets in a foreach loop, and the variables inside the brackets are local iterator variables. In your case, the first set of brackets are being treated as a state variable, whose value is always 0. Many people have incorrectly written code like

foreach(array[A]) {
    ...
    foreach(array[A][B]) {...} 
    }

expecting the inner foreach loop to only iterate over [B] while the outer foreach loop iterates over [A]. The correct and legal way of writing this is

foreach(array[A]) {
    ...
    foreach(array[,B]) {...} 
    }

and the correct and legal way of writing your constraint is

//int i,j,a,b; no need to. declare here as they are implicitly declared by foreach
constraint unique_elements {foreach (array[i,j]) {
    foreach (array[a,b]){
      (!(a==i && b==j)) -> array[a][b] != array [i][j];
    }
  }}