Clarification on usage of clocking block for inputs.
1800 says: 14.4 Input and output skews
Input (or inout) signals are sampled at the designated clock event. If an input skew is specified, then the signal is sampled at skew time units before the clock event.
Similarly, output (or inout) signals are driven
skew simulation time units after the corresponding clock event.
In assertions, 16.5.1 Sampling If a variable is an input variable of a clocking block, the variable shall be sampled by the clocking block with #1step sampling.
Question: Why would you want to sample the data x ns before the clocking event?
From an 1800 viewpoint, it is to provide flexibility in verification. For example, if a data point has a setup time of 2ns, the data must be stable 2ns before clocking it into a register. For verification, one could envision comparing a clocked output with data sampled 2ns before the clock edge and a clocked output with data sampled at the clock edge.
Usage example:
default clocking cb @(posedge clk);
default input #0 output #4 ;
input d1;
input #2 d2; // default to be 2 instead of 0
output reset;
endclocking
always @(cb or negedge reset)
begin
if (!reset)
begin
q1 <= 0;
q2 <= 0;
end
else
begin
q1 <= d2; // q1 is sampled at posedge clk
q2 <= cb.d2; // d2 is sampled 2ns prior to posedge clk
end
end
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