SystemVerilog Checker

SystemVerilog
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In reply to ben@SystemVerilog.us:

Hi Ben,

When I came back to digest the non-SVA solution, I realized that it will throw an error on the first {gotack,fallreq}. What is wrong with my understanding?

Here is the simplified example, the assertion failed on the first got_b is 0, not 1. I am surprised that got_b is not assigned successfully.

The code is put at:

Thanks,
mlsxdx